NES Emulator (First attempt)

Submitted by Logan Smyth on Tue, 12/30/2008 - 00:00

Tags 

vhdl, nes, emulator, fpga

I'd wanted to attempt an emulator forever, and at the beginning of the Fall 2008 semester, I was sitting at home, and realized that it would be a lot of fun to try and implement it in hardware. At the time, I was taking Digital System Design so had access to an FPGA board, the TerASIC DE1.

Being totally new to VHDL and hardware dev, I decided to start with the lowest end hardware I could think of, which was obviously the Nintendo Entertainment System. After a ton of research, I get a handle on a the basic hardware layout of the device.

At first I considered doing the CPU first, but since many games take advantage of the the timing being incredibly precise, I decided to use an IP core for it and focus on getting a system, then go back if time was available. Thus, I started work on the video rendering system, which proved to be very interesting.

One general thing with the design that I had to work around was getting the clock rate to line up. The VGA signal needs 25Mhz, and the CPU needs 2Mhz, and the PPU needs 6MHz. I ended up setting up a state machine to enable different states and make sure everything happened in the right order.

One other main design issue was that each device needs access to the RAM. The CPU and PPU in a real NES have their own memory, so they do not have to fight, but the DE1 only has one SRAM bank, and I did not want to have to deal with SDRAM.

After getting VGA working, I went to work programming the PPU. Many of the Wiki articles on the NesDev Wiki proved to be invaluable for this. The same goes for the NesDoc PDF file that I had. Before long I had the screen displaying the data stored in the video memory, as can be seen in the picture here. This is a photo of each graphic tile stored in the first of 2 graphic data tables in RAM. In this case I think it was Mario Brothers. It shows up in false color because it is reading the color from a dummy table.

After that the real diffuculty began, because I had to start making the hardware be able to scroll around and mirror data and wrap around the display. This proved a lot of work and took a while.

At this point, there wasn't much more I could do to debug issues, so I connected in the CPU IP core that I got online. I ended up having to modify it slightly, as it did not provide an enable pin, so I couldn't clock it correctly as it was.

With the CPU added, the unit was whole enough to execute code and modify the PPU's control registers, and based on test inputs, it seemed to do so correctly, but the full system never displayed correctly onscreen. :(

As a test, I threw together a quick test in Java to reimplement my hardware logic, to make sure I wasn't forgetting something. My java app was also unable to run a ROM game, however it did successfully execute and display a test ROM written by another emulator author as a test. This gives me a lot of hope that my design was very close. Unfortunately, in the end I had limited success due to lack of time. By this point, it was the end of the semester and I was forced to give the board back. The project was a success in that it hugely imploved my understanding of how hardware systems interact and process data, and it helped me understand interrupt systems, CPUs and hardware interactions very well.

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